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Retrieval & EmbeddingsHard· Performance· Memory Layout· SIMD
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See plansThe 5x gain is due to memory-layout changes: codes are transposed into blocks of 32 so one aligned load serves one subquantizer across the block. Additionally, 4-bit codebooks allow the table to fit the 16-entry in-register shuffle, and the table size drops from 16 KB to 512 bytes. It is not 30x because memory traffic on the code stream and top-k maintenance remain untouched, representing the gap between the theoretical instruction ratio and the measured performance.